Memory having read disturb test mode
US7719908B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Jan 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.