CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor
US7723174B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2009 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | May 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.