System for using test structures to evaluate a fabrication of a wafer
US7723724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2008 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Aug 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system is provided for using test structures to evaluate a fabrication of a wafer. The test structures include a combination of device and interconnect elements that are provided on an active region of a die, on the wafer prior to the fabrication of the wafer being completed. The combination of device and interconnect elements include one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics. A power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer. The one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits. A detector is provided to detect the output over the contactless medium, so as to receive the output without affecting a usability of the wafer when fabrication is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.