Stacked wafer or die packaging with enhanced thermal and device performance
US7723759B2 · kind B2 · utility
5Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Dec 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and the device layer, and a heat spreading and stress engineering region in the substrate and adjacent to the device layer. The via contacts a metal layer in the metallization region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.