Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips

US7723816B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gerald K. Bartley · Rochester, US
• Todd A. Christensen · Rochester, US
• Paul Eric Dahlen · Rochester, US
• John E. Sheets, II · Zumbrota, US

Key dates

• Filing date: Aug 6, 2008
• Grant date: May 25, 2010
• Expiry date: Oct 11, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/212

Abstract

A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.