Chip package without core and stacked chip package structure
US7723853B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 22, 2008 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Aug 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.