Memory device and method of refreshing
US7724567B2 · kind B2 · utility
3Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2008 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Sep 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.