System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US7724589B2 · kind B2 · utility
137Cited by
262References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 31, 2006 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.