Patent · US Active

Alignment of cache fetch return data relative to a thread

US7725659B2 · kind B2 · utility

2Cited by
8References
21Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 5, 2007
Grant dateMay 25, 2010
Priority date
Expiry dateNov 13, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F12/0859
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first sector in at least one alignment register, thereby permitting the at least first sector to be bypassed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.