Patent · US Active

System and method for layout optimization using model-based verification

US7725845B1 · kind B1 · utility

22Cited by

35References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

David White · San Jose, US
Roland Ruehl · Redwood City, US
Eric Nequist · Monte Sereno, US

Key dates

Filing date	Feb 24, 2007
Grant date	May 25, 2010
Priority date	—
Expiry date	Dec 23, 2027

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and system for chip optimization using model based verification (MBV) tool provide more accurate verification in determining hotspots and their characteristics. The MBV and the layout optimizer are implemented within a feedback loop. This type of verification allows for the MBV tool to provide hints, constraints and hotspot information to the layout optimizer. In addition, the model-based simulation results can be used to automatically fix the circuit designs and allow for specialized optimization flow for standard cell libraries.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.