Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US7727785B2 · kind B2 · utility
10Cited by
307References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to an opposite side from a stress-causing layer before the semiconductor die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.