COL-TSOP with nonconductive material for reducing package capacitance
US7728411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2006 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jan 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.