Memory device command decoding system and memory device and processor-based system using same
US7729191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Sep 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.