Parallel instruction processing and operand integrity verification
US7730346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Aug 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.