Interconnection structure of integrated circuit chip
US7732319B2 · kind B2 · utility
2Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.