Patent · US Active

Integrated circuit, method for manufacturing an integrated circuit, memory cell array, memory module, and device

US7732888B2 · kind B2 · utility

0Cited by

6References

28Claims

0Family size

Assignees

Qimonda AG · DE
Altis Semiconductor, SNC · FR

Inventors

Wolfgang Raberg · Sauerlach, DE
Cay-Uwe Pinnow · Birkenfeld, DE

Key dates

Filing date	Apr 16, 2007
Grant date	Jun 8, 2010
Priority date	—
Expiry date	Apr 18, 2028

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S438/90
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.