Chip carrier and fabrication method
US7733661B2 · kind B2 · utility
26Cited by
19References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2009 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Feb 25, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the first side. The passive component is formed free of the ground plane. An active component is attached to the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.