Circuit and method for optimizing memory sense amplifier timing
US7733711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Nov 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.