System and apparatus for using test structures inside of a chip during the fabrication of the chip
US7736916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Nov 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.