CMOS diodes with dual gate conductors, and methods for forming the same
US7737500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Oct 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/021
Abstract
The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.