Dual damascene integration of ultra low dielectric constant porous materials
US7737561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.