Programming a non-volatile memory device
US7738295B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device that has a cache register coupled between each pair of bit lines and, in one embodiment, a data cache coupled between each pair of bit lines. The cache register toggles a bit when a memory cell on one of the bit lines to which it is coupled is successfully programmed. The set bit inhibits further programming on that bit line. The data cache is programmed with the original data to be programmed in the particular memory cell coupled to the respective bit line. A programming method performs a programming/verification operation until the memory cell is programmed. The data cache is then read and this data is used in a secondary programming operation, after the initial programming/verification operation, on the same memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.