Three-dimensional package and method of making the same

US7741152B2 · kind B2 · utility

Assignee

• ADVANCED SEMICONDUCTOR ENGINEERING, INC. · TW

Inventors

• Min-Lung Huang
• Wei-Chung Wang · Tangxia, CN
• Po-Jen Cheng · Rancho Santa Fe, US
• Kuo-Chung Yee · Taipei, TW
• Ching-Huei Su
• Jian-Wen Lo
• Chian-Chi Lin · Tainan, TW

Key dates

• Filing date: Dec 26, 2006
• Grant date: Jun 22, 2010
• Expiry date: Nov 10, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.