Method of forming a semiconductor device having dummy features
US7741221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2005 |
| Grant date | Jun 22, 2010 |
| Priority date | — |
| Expiry date | Apr 19, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.