Patent · US Active

Leadframe and mold compound interlock in packaged semiconductor device

US7741704B2 · kind B2 · utility

11Cited by
4References
5Claims
0Family size

Assignees

Inventors

Key dates

Filing dateOct 18, 2007
Grant dateJun 22, 2010
Priority date
Expiry dateNov 27, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/18301
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.