Sequencer address management

US7743233B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Hong Wang · Santa Clara, US
• Gautham Chinya · Hillsboro, US
• Richard Hankins · San Jose, US
• Shivnandan Kaushik · Portland, US
• Bryant Bigbee · Scottsdale, US
• John Shen · Tainan, TW
• Per Hammarlund · Hillsboro, US
• Xiang Zou · Beaverton, US
• Jason W. Brandt · Austin, US
• Prashant Sethi · Folsom, US
• Douglas M. Carmean · Beaverton, US
• Baiju V. Patel · Portland, US
• Scott Dion Rodgers · Hillsboro, US
• Ryan Rakvic · Palo Alto, US
• John L. Reid · Portland, US
• David K. Poulsen · Champaign, US
• Sanjiv Shah · Champaign, US
• James P. Held · Portland, US
• James C. Abel · Anchorage, US

Key dates

• Filing date: Apr 5, 2005
• Grant date: Jun 22, 2010
• Expiry date: Dec 14, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/1009
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.