Patent · US Active

System and method for testing an integrated circuit

US7743295B2 · kind B2 · utility

1Cited by

7References

22Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Albrecht Mayer · Deisenhofen, DE
Klaus Scheibert · Grasbrunn, DE
Harry Siebert · Germering, DE

Key dates

Filing date	Mar 14, 2007
Grant date	Jun 22, 2010
Priority date	—
Expiry date	Oct 11, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0401
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface, wherein the volatile memory area is connected to the interface to be written thereto by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.