Semiconductor chip with stratified underfill
US7745264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2007 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Aug 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1433
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.