Method of making three dimensional NAND memory
US7745265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Aug 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.