Tri-gate patterning using dual layer gate stack

US7745270B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Uday Shah · Portland, US
• Brian S. Doyle · Portland, US
• Jack T. Kavalieros · Portland, US
• Been-Yih Jin · Lake Oswego, US

Key dates

• Filing date: Dec 28, 2007
• Grant date: Jun 29, 2010
• Expiry date: May 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.