Impurity control in HDP-CVD DEP/ETCH/DEP processes
US7745350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2008 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A first portion of the silicon oxide film is deposited over the substrate and within the gap using a high-density plasma process. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched back. This includes flowing a halogen precursor through a first conduit from a halogen-precursor source to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the portion has been etched back. Thereafter, a halogen scavenger is flowed to the substrate processing chamber to react with residual halogen in the substrate processing chamber. Thereafter, a second portion of the silicon oxide film is deposited over the first portion of the silicon oxide film and within the gap using a high-density plasma process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.