Bus having a dynamic timing bridge
US7747889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Jun 29, 2010 |
| Priority date | — |
| Expiry date | Jan 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.