Robert N. Ehrlich
10Patents
3h-index
14Co-inventors
49Inventor score
Filing activity: Jul 31, 2006 → Dec 11, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8601315B2 | Debugger recovery on exit from low power mode | Physics | 10 | Active |
| US9366724B1 | Scan testing with staggered clocks | Physics | 4 | Active |
| US7793025B2 | Hardware managed context sensitive interrupt priority level control | Physics | 4 | Active |
| US8572323B2 | Cache result register for quick cache information lookup | Physics | 1 | Active |
| US9304880B2 | System and method for multicore processing | Physics | 1 | Active |
| US8666690B2 | Heterogeneous multi-core integrated circuit and method for debugging same | Physics | 0 | Active |
| US9626280B2 | Debug method and device for handling exceptions and interrupts | Physics | 0 | Active |
| US7747889B2 | Bus having a dynamic timing bridge | Electricity | 0 | Active |
| US9495169B2 | Predicate trace compression | Physics | 0 | Active |
| US9626279B2 | Debug method and device for providing indexed trace messages | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.