Fabricating method of non-volatile memory cell
US7749838B2 · kind B2 · utility
1Cited by
12References
10Claims
0Family size
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Key dates
| Filing date | Jul 6, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Apr 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.