High electron mobility transistor having self-aligned miniature field mitigating plate on a protective dielectric layer
US7750370B2 · kind B2 · utility
4Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Feb 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.