Patent · US Active

Wafer level test probe card

US7750651B2 · kind B2 · utility

11Cited by
10References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 3, 2008
Grant dateJul 6, 2010
Priority date
Expiry dateJun 4, 2028

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10T29/49222
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.