Interconnect structure and method in programmable devices
US7750673B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Oct 27, 2005 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Jan 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved interconnect structure in programmable devices gives a new dimension to the routing architecture, where architecture is divided into various domains. It includes at least one set of input lines, each set having predetermined number of input lines; an equal number of sets of routing lines, each set of routing lines being connected to a corresponding set of input lines using a switch box; thereby forming domain based routing structures, each domain being disjoint with the other domain. Segregating FPGA routing resources into various independent routing domains is done; each domain providing connectivity to route a signal to a set of sinks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.