Manuj AYODHYAWASI
15Patents
1h-index
12Co-inventors
47Inventor score
Filing activity: Oct 27, 2005 → Oct 17, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US12087356B2 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US11984151B2 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US12237007B2 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12361982B2 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Physics | 0 | Active |
| US11900240B2 | Variable clock adaptation in neural network processors | Emerging Cross-Sectional Technologies | 0 | Active |
| US11836346B2 | Tagged memory operated at lower vmin in error tolerant system | Emerging Cross-Sectional Technologies | 0 | Active |
| US12183424B2 | Bit-cell architecture based in-memory compute | Physics | 0 | Active |
| US12170120B2 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Physics | 0 | Active |
| US12354644B2 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12386506B2 | Tagged memory operated at lower VMIN in error tolerant system | Emerging Cross-Sectional Technologies | 0 | Active |
| US11360667B2 | Tagged memory operated at lower vmin in error tolerant system | Emerging Cross-Sectional Technologies | 0 | Active |
| US12406705B2 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Physics | 0 | Active |
| US12353341B2 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Physics | 0 | Active |
| US7750673B2 | Interconnect structure and method in programmable devices | Electricity | 0 | Expired |
| US12176025B2 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.