CMOS back-gated keeper technique
US7750682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Mar 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.