Timing control circuit, timing generation system, timing control method and semiconductor memory device
US7750712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2008 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Feb 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00241
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.