Late data launch for a double data rate elastic interface
US7752475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2006 |
| Grant date | Jul 6, 2010 |
| Priority date | — |
| Expiry date | Oct 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.