Method for packaging microelectronic devices
US7754531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2006 |
| Grant date | Jul 13, 2010 |
| Priority date | — |
| Expiry date | Jun 1, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49222
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.