Memory device and fabrication method thereof
US7759190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
Abstract
A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on the substrate and neighboring the trench. An opening is formed on the substrate between the collar dielectric layer and the gate structure. Next, a portion of the top dielectric layer and the collar dielectric layer is removed to expose a portion of the conductive column. An insulating layer is deposited on the gate structure and the exposed conductive column, filling the opening. The insulating layer is etched to expose a portion of the capacitor-side region of the substrate and the conductive column. A transmissive strap is formed by selective deposition, electrically connecting the capacitor-side region of the substrate and the conductive column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.