Semiconductor package having structure for warpage prevention
US7759807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Aug 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure covering an upper surface of the substrate including a connection region between the bonding pads and the connection pads and the semiconductor chip; a second molding structure formed adjacent to an edge of the lower surface of the substrate; and a plurality of solder balls attached to the respective ball lands of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.