Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US7761724B2 · kind B2 · utility
136Cited by
321References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Apr 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.