Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations

US7763505B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Andreas Gehring · Dresden, DE
• Markus Lenski · Dresden, DE
• Jan Hoentschel · Dresden, DE
• Thorsten Kammler · Radeberg, DE

Key dates

• Filing date: Apr 25, 2007
• Grant date: Jul 27, 2010
• Expiry date: Sep 24, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.