Inventor · Dresden, DE

Markus Lenski

58Patents
9h-index
70Co-inventors
77Inventor score

Filing activity: Nov 12, 2004 → Jun 22, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US10483154B1 Front-end-of-line device structure and method of forming such a front-end-of-line device structure Electricity 375 Active
US7741663B2 Air gap spacer formation Emerging Cross-Sectional Technologies 54 Active
US8071442B2 Transistor with embedded Si/Ge material having reduced offset to the channel region Electricity 19 Active
US7354838B2 Technique for forming a contact insulation layer with enhanced stress transfer efficiency Electricity 17 Active
US7943462B1 Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer Electricity 12 Active
US7208397B2 Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same Electricity 12 Expired
US7754556B2 Reducing transistor junction capacitance by recessing drain and source regions Electricity 12 Active
US7763505B2 Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations Electricity 10 Active
US7981740B2 Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning Electricity 9 Active
US8349694B2 Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy Electricity 8 Active
US7109086B2 Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique Electricity 6 Expired
US8367495B2 Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material Electricity 5 Active
US8298894B2 Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layer Electricity 5 Active
US8815674B1 Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions Electricity 4 Active
US7754555B2 Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode Electricity 3 Active
US8227266B2 Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions Electricity 3 Active
US8765542B1 Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions Electricity 3 Active
US8383500B2 Semiconductor device formed by a replacement gate approach based on an early work function metal Electricity 3 Active
US8652917B2 Superior stability of characteristics of transistors having an early formed high-K metal gate Electricity 3 Active
US7713763B2 Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions Electricity 3 Active
US8357573B2 Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode Electricity 3 Active
US7879667B2 Blocking pre-amorphization of a gate electrode of a transistor Electricity 2 Active
US8871586B2 Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material Emerging Cross-Sectional Technologies 2 Active
US8173501B2 Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition Electricity 2 Active
US8198166B2 Using high-k dielectrics as highly selective etch stop materials in semiconductor devices Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.