Method for making an integrated circuit including vertical junction field effect transistors

US7763506B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Michael Treu · Villach, AT
• Roland Rupp · Achern, DE
• Heinz Mitlehner · Uttenreuth, DE
• Rudolf Elpelt · Erlangen, DE
• Peter Friedrichs · Koblenzer Straße, DE
• Larissa Wehrhahn-Kilian · Erlangen, DE

Key dates

• Filing date: Sep 10, 2007
• Grant date: Jul 27, 2010
• Expiry date: Sep 10, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.