Method for PFET enhancement
US7763510B1 · kind B1 · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2009 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
Abstract
A semiconductor process and apparatus includes forming PMOS transistors (90) with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer (91, 136) on or adjacent to sidewalls of the PMOS gate structure as either a hydrogen-rich implant sidewall spacer (91) or as a post-silicide hydrogen-rich implant sidewall spacer (136), where the hydrogen-rich dielectric layer acts as a hydrogen source for passivating channel surface defectivity under the PMOS gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.