Three-dimensional integrated C-MOS circuit and method for producing same

US7763915B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Jean-Pierre Joly · Golbey, FR
• Olivier Faynot · Seyssinet-Pariset, FR
• Laurent Clavelier · Grenoble, FR

Key dates

• Filing date: Jan 18, 2007
• Grant date: Jul 27, 2010
• Expiry date: Jun 7, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.